FSB is the hard-to-build frequency of CPy:

• A.which directly determines the degree of data exchange between CPU and memory.
• B.the unit is the external frequency of MHZ CPU,

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Common instruction sets of microprocessors include reduced instruction set, complex instruction set, display parallel instruction set, etc. The following statement about instruction set is correct.

• A.The super-long instruction word instruction set integrates multiple instructions into one instruction word, which effectively improves the utilization efficiency of each computing function component of the CPU and improves the performance of the program
• B.The reduced instruction set reduces the number of instructions and the addressing mode, making it easier to implement, and the parallel execution of instructions is better. The compiler is more efficient.
• C.Show that the parallel instruction set allows the processor to execute instructions in parallel according to the schedule of the compiler without increasing the complexity of the hardware. The architecture is developed from the super long instruction frame and made a lot of improvements
• D.In the complex instruction set microprocessor, each instruction of the program is executed in sequence, and each operation in each instruction is also executed by the authorized management bank.

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Which of the following processor types belong to the RISC instruction set architecture?

• A.MIPS
• B.POWERPC
• C.ARM
• D.X86

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The author of "Secret History of Silicon Valley", steveBlabnk, the father of Lean Entrepreneurship, wrote in
2018 that Moore's Law has been effective as early as ten years ago, but consumers have not yet noticed it. The following analysis of Moore's Law is correct.

• A.Process technology upgrade to technical bottleneck
• B.Multi-core single-chip Moore's Law, but multi-core performance improvement is difficult to be used by software
• C.The main frequency cannot be increased, the power consumption will also increase dramatically
• D.The cost of a chip manufacturing plant doubles every 4 years

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The cache size is also one of the important indicators of the CPU and the structure and size of the cache have a great impact on the CPU speed. The following statement about the CPU cache is wrong.

• A.The second level cache is the second level cache of the CPU, which is divided into internal and external chips
• B.Level 3 cache is a type of cache designed for data that misses after reading level 2 cache
• C.The CPU cache is divided into three levels, the most important of which is the level three cache, where
  80% of the data is stored.
• D.The first-level cache is the CPU layer-1 cache, which has the highest technical difficulty and manufacturing cost, and is divided into data cache and instruction cache

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